Jan 16, 2025

—Second in a three-part series. You can read the first article here While there are hundreds of companies that adopt Arm technology, not many of them develop their own custom cores. Something similar will likely happen in the case of RISC-V: companies that need a very specific core and control of their firmware and software stack will be more inclined to design a core from scratch. For example, Seagate and Western Digital use custom RISC-V cores for their storage controllers. Companies that need to run a lot of off-the-shelf software will prefer off-the-shelf cores or even Arm or x86 CPUs. Meta’s custom MSVP RISC-V-based ASIC for video transcoding. (Source: Meta) “Designing your own core can make sense in certain niche/edge cases,” Ian Ferguson, senior director at SiFive, told EE Times. “At a high level, this is driven by whether you need to customize instructions or have a specific design to own the entire software stack for competitive differentiation reasons.” Partner Content By Stephen Las Marias, EE Times Asia   01.08.2025 This opinion is not shared by Ventana Micro. For use cases like AI and HPC , building a custom core optimized for a particular workload and data types on top of standard vector extension can bring major performance benefits—especially when compared to Arm-based implementations. “In the end it is a multifactor ROI,” said a spokesperson for Ventana Micro. “You get something you can 10× or more optimized to your workload years earlier, at a lower cost assuming you are starting with an existing baseline RISC-V design.” “Customizing cores is the logical extension of upgrading traditional server platforms,” said James Prior, marketing executive at MIPS, in an interview with EE Times. “For most AI/HPC data center installations, the primary concern is performance per watt and delivering the computational results as fast as possible. The benefits of creating custom platforms with specific workload acceleration may be reduced time to complete training a model, increased tokens per second for inference, lower token per watt, or lower peak cooling and power requirements.” “[The question is whether to] ‘build in-house’ or ‘license with customizations,’” Roger Espasa, CEO of SemiDynamics, told EE Times. “In many cases, ‘license-with-customizations’ will cut 3-plus years of your development time and, hence, is the right way to go.” For large hyperscalers , designing a custom RISC-V core could enable some major advantages and lower costs compared to off-the-shelf Arm cores. Meta has yet to share benefits that the company received from deploying its RISC-V-based MSVP (video processor) and MTIA (training and inference accelerators) processors. But the very fact that it keeps procuring Nvidia’s data center GPUs indicates that its own RISC-V chips cannot cover all of its requirements. “[The actual value created by a custom RISC-V core] depends on the key value proposition of the platform. But typically if the purpose designed core based on RISC-V was able to offer 20% less area use, then every instance of the use could be 20% lower cost,” MIPS’ Prior said. “In a system scaling to millions of devices, this can translate into very large savings.” However, potential savings and costs of implementing and supporting a highly custom core must be accurately assessed, according to Red Semiconductor. “[Savings can be] one-third [compared to an off-the-shelf Arm core],” said David Harold, head of business development at Red Semiconductor, in an interview with EE Times. “But it is not just about cost of licensing the core. The engineer must consider the on-costs of use of the core on the SoC—energy, time and silicon resources to accomplish a processing task, as well as designing and writing code. All of these can be optimized with VISC.” If a company wants to develop a processor core from the ground up, it can do so. Though SiFive’s Ferguson believes that many companies would prefer to license a commercial CPU IP and focus their development efforts on their own value-adding IP. “For the majority of use cases, we believe companies will want to rely on a high quality, high performance third-party implementation, which gives you much better value and time to market,” Ferguson said. “Many companies wish to focus their value add elsewhere so we expect the majority of companies to build their systems by harnessing CPU core building blocks from providers of commercial IP and/or silicon.” Working with a proven supplier is a good way to reduce risks typically associated both with custom chip designs in general and with RISC-V in particular. “A new technology is always a risk,” Thomas Hackenberg, principal analyst for the memory and computing division at Yole Development, told EE Times. “There is a risk of an emerging supplier going out of business and not supporting its product. The technology might change more rapidly than expected, leaving early adopters with inferior solutions. With designs mainly supported by communities with a mix of volunteers and professionals, support can be iffy. The level of engineering expertise from an incumbent supplier like Arm could adapt and develop extensions that make custom RISC-V solutions irrelevant. There are many additional risks, but RISC-V development is unlikely to disappear in the foreseeable future.” Cost and performance per watt advantage RISC-V certainly gives a lot of flexibility for chip designers, but many companies adopt this instruction set architecture (ISA) due to cost concerns. With Arm’s latest pricing policies, the technology gets more expensive to adopt, so RISC-V gets more attractive. But beyond just the cost of licenses, there are other factors that make RISC-V appealing, which include simpler architecture, lower die sizes and lower power. “First of all, [RISC-V] licenses [for pre-developed cores] are much cheaper than Arm,” SemiDynamics’ Espasa said. “Second, the overall architecture is simpler, so an experienced SoC team will be able to glue together their solution faster. Third, you can mix-and-match solutions from different vendors (which gives you negotiation power) and still have a single, unified software stack. Having said all that, building an SoC is always a challenging task, but RISC-V certainly helps you quite a bit.” As RISC-V is an open-source ISA, there is no need to pay a license fee for the instruction set itself. “If you want Arm, you have to pay a license and a royalty,” said Karl Freund, founder and principal analyst at Cambrian AI. Freund. “[It is] not so with RISC-V, and [this] is one reason it is so popular in China.” Meta’s MTIA inference accelerator. (Source: Meta) But while saving on license and royalty fees is important for companies that produce millions of chips, performance per watt and ability to tailor performance, power and die size to the needs of a particular application due to customizability of RISC-V in general is perhaps a much more important aspect—both for startups and for established players. There are two reasons why a RISC-V-based core may have performance per watt advantages over a core based on an established ISA: it does not have legacy from prior generations it is mandated to carry, and it can be tailored for a particular application. “Compared with Arm and x86, [SiFive’s cores] show performance/watt advantages against Arm CPUs,” SiFive’s Ferguson said. “This comes from two factors. [RISC-V] is a modern instruction set so there is no legacy from prior generations. In side-by-side comparisons to mid-range processor cores like Arm’s Cortex-A78, SiFive offers more performance for equivalent power or comparable performance for dramatically less power. Other companies in the RISC-V ecosystem are offering processors with a similar value proposition at different points on the performance spectrum. [Another factor is] selective definition and inclusion of new instructions to support the effective implementation of emerging applications.” “RISC-V is usually acclaimed by its users for its higher efficiency compared to traditional microprocessors: in comparison to ARM and x86, RISC-V is potentially providing a 3× advantage in computational performance per power,” said Christophe Bianchi, CTO at Ansys, in an interview with EE Times. Ferguson admits that nowadays, RISC-V cores are slower in terms of single-thread performance compared to Arm and x86. But since they are smaller and less power hungry, chip designers can integrate more of these cores into their processors, which will provide an advantage in multi-threaded applications. “There is a gap between RISC-V and incumbent architectures in terms of single thread performance,” Ferguson said. “But the die size and power advantages of RISC-V enable more CPU cores to be packed into a given die size and/or power target, so the aggregate throughput of a RISC-V based chip is higher than something created from an incumbent architecture.”